1. Field of the Invention
The present invention relates to a semiconductor integrated device, and particularly to a memory device called SRAM (Static Random Access Memory).
2. Description of the Related Art
SRAM as a semiconductor integrated device comprises a plurality of memory cells, and each memory cell is connected to a pair of bit lines. Via the pair of bit lines, bit information indicating whether an electric potential exists is written into the memory cell, and bit information held in the memory cell is read out. Such write and read access to the memory cell is performed after applying a potential called pre-charge to the pair of bit lines. The memory cell can be accessed at high speed by having pre-charged. As mentioned above, after having pre-charged, bit information read out from the memory cell is output via an output section. Such semiconductor devices are disclosed in Japanese Patent Laid-Open Publication No. 11-86561 and Japanese Patent Laid-Open Publication No. 11-353880.
In a conventional semiconductor integrated device, for example, when reading out bit information from a memory cell, one bit line transmits bit information indicating a high potential, while the other bit line transmits bit information indicating a low potential. That is, an electric potential is released to discharge electric charges applied to one bit line of the bit line pair pre-charged beforehand. Hence, in the next access to a memory cell, electric charges need to be applied again by pre-charging beforehand.
Because charging and discharging a pair of bit lines is repeated as described above, the reduction of power consumption has been required of semiconductor integrated devices. There is also the problem that the output section operates increasing consumption current, even when writing bit information into the memory cell.